Field
Implementations of the disclosure generally relate to the field of semiconductor manufacturing processes and devices, more particularly, to methods for epitaxial growth of a silicon material on an epitaxial film.
Description of the Related Art
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 22 nm or smaller dimensions, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. Recently, complementary metal oxide semiconductor (CMOS) FinFET devices have been widely used in many logic and other applications and are integrated into various different types of semiconductor devices.
FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed thereover. A gate electrode is then formed over and along side of a portion of the fin devices utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. Further advantages of FinFETs include reducing the short channel effect and providing higher current flow.
To improve transistor performance, stressor materials may fill source/drain areas, and the stressor materials may grow in source/drain areas by epitaxy. The epitaxial film is faceted by {111} planes and has a diamond shape along the transistor channel direction. With the scaling down of transistors, there is always a need for improved methods for forming FinFETs.